The development of electronic devices with layered interconnects, such as printed circuit boards or integrated circuit packages, usually involves many steps, known as a design flow. This design flow typically starts with a specification for a new circuit to be implemented with a layered interconnect. The specification of the new circuit can be transformed into a circuit design, such as a netlist, for example, by a schematic capture tool or by synthesizing a logical circuit design, sometimes referred to as a register transfer level (RTL) description of the circuit. The netlist, commonly specified in an Electronic Digital Exchange Format (EDIF), can describe nets or connectivity between various devices or instances in the circuit design.
The design flow continues by verifying functionality of the circuit design, for example, by simulating or emulating the circuit design and verifying that the results of the simulation or emulation correspond with an expected output from the circuit design. The functionality also can be verified by statically checking the circuit design for various attributes that may be problematic during operation of an electronic device built utilizing the circuit design.
Once the circuit design has been functionally verified, the design flow continues to design layout and routing, which includes placing and interconnecting various components into a representation of a layered interconnect in order to generate a layout design of the electronic device implemented in the layered interconnect. This procedure can be implemented in many different ways, but typically, through the use of a layout tool, which can present at least one graphical view of the layered interconnect and allow a designer to drag or place parts from a library onto the layered interconnect.
After generation of the layout design of the electronic device implemented with the layered interconnect, the design flow can verify the layout design of the electronic device implemented with the layered interconnect. Some layout verification analysis includes an evaluation of signal integrity on signaling nets in the layout design. Typically, the signaling nets in the layout design can be converted into an electrical model, such as scattering parameters (S-Parameters), which can subsequently be utilized to evaluate the signal integrity on the signaling nets in the layout design.
Due to the size and complexity of the modern layout designs, conversions of the signaling nets in the layout design into the electrical models typically utilize a divide-and-conquer methodologies, for example, in which smaller via transition regions can be analyzed by a computationally-expensive three-dimensional field solver and the much larger routing areas can be analyzed using cascaded transmission line models. These divide-and-conquer methodologies crop out portions of the layout design and generate electrical models for each cropped portion.
The divide-and-conquer methodologies can implement a mesh generation process to generate mesh elements for surface areas of each of the cropped portion of the layout design. The mesh elements can correspond to geometric shapes, such as rectangles, squares, triangles, or the like, on the surface area of the cropped portion of the layout design. The divide-and-conquer methodologies often utilize field solvers, for example, implementing a finite element method (FEM) analysis or a finite difference time-domain (FDTD) analysis to generate the electrical model for the signaling nets in the layout design by solving differential forms of Maxwell's equations.
Since the divide-and-conquer methodologies crop the layout design, the field solvers can generate an electrical model for a cropped portion of signaling nets in the layout design that includes artificial reflection arising from the cropped planes implementing the signaling nets. In other words, the field solvers generate the electrical model as if the signaling plane was actually severed where the divide-and-conquer methodologies cropped it. The field solvers implementing FEM-based analysis or FDTD-based analysis often truncate open or unbounded areas in order simplify the differential forms of Maxwell's equations to be solved, for example, by utilizing techniques, such as an absorbing boundary condition (ABC), a perfectly matched layer (PML), or lossy padding, so the divide-and-conquer methodologies utilizing field solvers implementing FEM-based analysis or FDTD-based analysis typically add absorbent materials outside of the cropped edges of the signaling nets being analyzed. The utilization of these absorbent materials, however, is complicated, time-consuming and resource-intensive as well as less amenable to automation due to the difficulty in eliminating geometrical conflicts with existing signaling net planes in the layered interconnect.